Conserving power by reducing voltage supplied to an instructions-processing portion of a processor

ABSTRACT

One embodiment of the present invention provides a system that facilitates reducing static power consumption of a processor. During operation, the system receives a signal indicating that instruction execution within the processor is to be temporarily halted. In response to this signal, the system halts an instruction-processing portion of the processor, and reduces the voltage supplied to the instruction-processing portion of the processor. Full voltage is maintained to a remaining portion of the processor, so that the remaining portion of the processor can continue to operate while the instruction-processing portion of the processor is in reduced power mode.

BACKGROUND

Field of the Invention

The present invention relates to techniques for conserving power usagein computer systems. More specifically, the present invention relates toa method and an apparatus for reducing power consumption in a processorby reducing voltage supplied to an instruction-processing portion of theprocessor, while maintaining voltage to other portions of the processor.

Related Art

Dramatic advances in integrated circuit technology have led tocorresponding increases in processor clock speeds. Unfortunately, theseincreases in processor clock speeds have been accompanied by increasedpower consumption. Increased power consumption is undesirable,particularly in battery-operated devices such as laptop computers, forwhich there exists a limited supply of power. Any increase in powerconsumption decreases the battery life of the computing device.

Modern processors are typically fabricated using Complementary MetalOxide Semiconductor (CMOS) circuits. CMOS circuits typically consumemore power while the circuits are switching, and less power while thecircuits are idle. Designers have taken advantage of this fact byreducing the frequency of (or halting) clock signals to certain portionsof a processor when the processor is idle. Note that some portions ofthe processor must remain active, however. For example, a cache memorywith its associated snoop circuitry will typically remain active, aswell as interrupt circuitry and real-time clock circuitry.

Although reducing the frequency of (or halting) a system clock signalcan reduce the dynamic power consumption of a processor, static powerconsumption is not significantly affected. This static power consumptionis primarily caused by leakage currents through the CMOS devices. Asintegration densities of integrated circuits continue to increase,circuit devices are becoming progressively smaller. This tends toincrease leakage currents, and thereby increases static powerconsumption. This increased static power consumption results in reducedbattery life, and increases cooling system requirements for batteryoperated computing devices.

What is needed is a method and an apparatus that reduces static powerconsumption for a processor in a battery operated computing device.

SUMMARY

One embodiment of the present invention provides a system thatfacilitates reducing static power consumption of a processor. Duringoperation, the system receives a signal indicating that instructionexecution within the processor is to be temporarily halted. In responseto this signal, the system halts an instruction-processing portion ofthe processor, and reduces the voltage supplied to theinstruction-processing portion of the processor. Full voltage ismaintained to a remaining portion of the processor, so that theremaining portion of the processor can continue to operate while theinstruction-processing portion of the processor is in reduced powermode.

In one embodiment of the present invention, reducing the voltagesupplied to the instruction-processing portion of the processor involvesreducing the voltage to a minimum value that maintains state informationwithin the instruction-processing portion of the processor.

In one embodiment of the present invention, reducing the voltagesupplied to the instruction-processing portion of the processor involvesreducing the voltage to zero.

In one embodiment of the present invention, the system saves stateinformation from the instruction-processing portion of the processorprior to reducing the voltage supplied to the instruction-processingportion of the processor. This state information can either be saved inthe remaining portion of the processor or to the main memory of thecomputer system.

In one embodiment of the present invention, upon receiving a wakeupsignal, the system: restores full voltage to the instruction-processingportion of the processor; restores state information to theinstruction-processing portion of the processor; and resumes processingof computer instructions.

In one embodiment of the present invention, maintaining full voltage tothe remaining portion of the processor involves maintaining full voltageto a snoop-logic portion of the processor, so that the processor cancontinue to perform cache snooping operations while theinstruction-processing portion of the processor is in the reduced powermode.

In one embodiment of the present invention, the system also reduces thevoltage to a cache memory portion of the processor. In this embodiment,the system writes cache memory data to main memory prior to reducing thevoltage.

In one embodiment of the present invention, the remaining portion of theprocessor includes a control portion of the processor containinginterrupt circuitry and clock circuitry.

In one embodiment of the present invention, the remaining portion of theprocessor includes a cache memory portion of the processor.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1A illustrates different power areas within processor 102 inaccordance with an embodiment of the present invention.

FIG. 1B illustrates alternate power areas within processor 102 inaccordance with an embodiment of the present invention.

FIG. 2 is a flowchart illustrating the process of monitoring processorload and switching to power saving modes in accordance with anembodiment of the present invention.

DETAILED DESCRIPTION

The following description is presented to enable any person skilled inthe art to make and use the invention, and is provided in the context ofa particular application and its requirements. Various modifications tothe disclosed embodiments will be readily apparent to those skilled inthe art, and the general principles defined herein may be applied toother embodiments and applications without departing from the spirit andscope of the present invention. Thus, the present invention is notintended to be limited to the embodiments shown, but is to be accordedthe widest scope consistent with the principles and features disclosedherein.

Processor

FIG. 1A illustrates different power areas within processor 102 inaccordance with an embodiment of the present invention. Processor 102 isdivided into a core power area 126, and a non-core power area 124. Corepower area 126 includes the instruction-processing portion of processor102. Specifically, core power area 126 includes arithmetic-logic unit104, register files 106, pipelines 108, and possibly level one (L1)caches 110. Note that L1 caches 110 can alternatively be located innon-core power area 124.

Arithmetic-logic unit 104 provides computational and logical operationsfor processor 102. Register files 106 provide source operands,intermediate storage, and destination locations for instructions beingexecuted by arithmetic-logic unit 104. Pipelines 108 provides a steadystream of instructions to arithmetic-logic unit 104. Instructions inpipelines 108 are decoded in transit. Therefore, pipelines 108 maycontain instructions in various stages of decoding and execution. L1caches 110 include data caches and instruction caches forarithmetic-logic unit 104. L1 caches 110 are comprised of veryhigh-speed memory to provide fast access for instructions and data. Inone embodiment of the present invention, L1 caches 110 includes awrite-through data cache.

Non-core power area 124 comprises the remaining portion of processor 102and includes interrupt processor 112, real-time clock 114, clockdistribution circuitry 116, level two (L2) caches 118, cache tags 120,and cache snoop circuitry 122. In general, non-core power area 124includes portions of processor 102 that are not directly involved inprocessing instructions, and that need to operate while instructionprocessing is halted.

Interrupt processor 112 monitors interrupts 128 and periodicallyinterrupts the execution of applications to provide services to externaldevices requiring immediate attention. Interrupt processor 112 can alsoprovide a wake-up signal to core power area 126 as described below.Real-time clock 114 provides time-of-day services to processor 102.Typically, real-time clock 114 is set upon startup from a batteryoperated real-time clock in the computer and thereafter provides time tothe system. Clock distribution circuitry 116 provides clock signals forprocessor 102. Distribution of these clock signals can be switched offor reduced for various parts of processor 102. For example, clockdistribution to core power area 126 can be stopped while the clocksignals to non-core power area 124 continue. The acts of starting andstopping of these clock signals are known in the art and will not bedescribed further. Real-time clock 114 and clock distribution circuitry116 receive clock signal 130 from the computer system. Clock signal 130is the master clock signal for the system.

L2 cache 118 provides a second level cache for processor 102. Typically,an L2 cache is larger and slower that an L1 cache, but still providesfaster access to instructions and data than can be provided by mainmemory. Cache tags 120 provide an index into data stored in L2 cache118. Cache snoop circuitry 122 invalidates cache lines base primarily onother processors accessing their own cache lines, or I/O devices doingmemory transfers, even when instruction processing has been halted. L2cache 118, cache tags 120, and cache snoop circuitry 122 communicatewith the computer system through memory signals 132.

Non-core power area 124 receives non-core power 136 and core power area126 receives core power 134. The voltage applied for non-core power 136remains at a voltage that allows circuitry within non-core power area124 to remain fully active at all times. In contrast, non-core power 136may provide different voltages to non-core power area 124 based upon theoperating mode of processor 102. For example, if processor 102 is alaptop attached to external electrical power, the voltage provided tonon-core power 136 (and to core power 134 during instruction processing)may be higher than the minimum voltage, thus providing faster executionof programs.

The voltage applied to core power 134 remains sufficiently high duringinstruction processing so that core power area 126 remains fully active.However, when processor 102 receives a signal that processing can besuspended, the voltage supplied by core power 134 can be reduced.

In one embodiment of the present invention, the voltage in core power134 is reduced to the minimum value that will maintain state informationwithin core power area 126, but this voltage is not sufficient to allowprocessing to continue. In another embodiment of the present invention,the voltage at core power 134 is reduced to zero. In this embodiment,the state of core power area 126 is first saved before the voltage isreduced to zero. This state can be saved in a dedicated portion of L2cache 118, in main memory, or in another dedicated storage area. Uponreceiving an interrupt or other signal indicating that processing is toresume, the voltage in core power 134 is restored to a normal level,saved state is restored, and processing is restarted.

FIG. 1B illustrates an alternative partitioning of power areas withinprocessor 102 in accordance with an embodiment of the present invention.As shown in FIG. 1B, L2 cache 118, cache tags 120, and cache snoopcircuitry 122 are included in core power area 126 rather than innon-core power area 124. In this embodiment, the voltage supplied ascore power 134 is reduced or set to zero as described above, however,the cache circuitry within processor 102 is also put into the reducedpower mode. Prior to reducing the voltage supplied to core power area126, data stored in L2 cache 118 is flushed to main memory.Additionally, if the voltage at core power 134 is reduced to zero, thestate of processor 102 is first saved in main memory.

Monitoring and Switching

FIG. 2 is a flowchart illustrating the process of monitoring processorload and switching to power saving modes in accordance with anembodiment of the present invention. The system starts by monitoring theprocessor load (step 202). Next, the system determines if the processorwill be needed soon (step 204). This determination is made based on thecurrent execution pattern and the cost of entering and recovering fromnap mode. This cost, calculated in power usage, must be less than thepower wasted by not going into nap mode. If the processor will be neededsoon at step 204, the process returns to step 202 to continue monitoringthe processor load.

If the processor will not be needed soon at step 204, the systemdetermines if the processor has been taking long naps recently (step206). If not, the system enters a normal nap mode, which involveshalting the processor without reducing any voltages (step 208).Typically, halting the processor involves removing the clock signals tothe core power area of the processor. After halting the processor, thesystem waits for an interrupt (step 210). Upon receiving an interrupt orother signal requiring a restart, the system restarts instructionprocessing (step 212). After restarting instruction processing, theprocess returns to step 202 to continue monitoring the processor load.

If the processor has recently been taking long naps at step 206, thesystem enters a deep nap mode, which involves saving the stateinformation from the core power area (step 214), halting the processor(step 216), and then reducing the voltage supplied to the core powerarea (step 218). After reducing the voltage, the system waits for aninterrupt (step 220).

Upon receiving the interrupt or other signal requiring a restart, thesystem restores the voltage to the core power area (step 222). Next, themodules within the core power area are restarted (step 224). The systemthen restores the state information that was saved at step 214 (step226). After the processor has been restarted, the process returns tostep 202 to continue monitoring the processor load. Note that the abovedescription applies when the processor is used to save and restore thestate information. In cases where dedicated hardware saves and restoresthe state information, steps 214 and 216, and steps 224 and 226 can bereversed. Note also that if the voltage supplied to the core power area126 is reduced but maintained at a level where modules in the core powerdo not lose state information, steps 216 and 224 are not required.

The foregoing descriptions of embodiments of the present invention havebeen presented for purposes of illustration and description only. Theyare not intended to be exhaustive or to limit the present invention tothe forms disclosed. Accordingly, many modifications and variations willbe apparent to practitioners skilled in the art. Additionally, the abovedisclosure is not intended to limit the present invention. The scope ofthe present invention is defined by the appended claims.

What is claimed is:
 1. A processor, comprising: a first power area thatcomprises an instruction-processing portion of the processor andoperates responsive to a first voltage and a first clock signal that aresupplied to the first power area; and a second power area that comprisesa second portion of the processor and operates responsive to a secondvoltage that is supplied to the second power area; wherein the firstpower area of the processor operates in one of a normal operation modewhen the first voltage is at a first level, a first power-saving modewhen the first voltage is at a second level, and a second power-savingmode when the first voltage is at a third level; and wherein the firstpower area of the processor is configured to transition from the normaloperation mode to the first or second power saving mode based, at leastin part, on a comparison of a cost of entering and exiting from thefirst or second power saving mode with a cost of remaining in the normaloperation mode.
 2. The processor of claim 1, wherein in the normaloperation mode: the first clock signal is active; the first voltage issufficient for the instruction-processing portion of the processor toprocess instructions; and the second voltage is sufficient for thesecond portion of the processor to operate.
 3. The processor of claim 2,wherein in the first power-saving mode: the first clock signal isinactive; the first voltage is sufficient to maintain a state of theinstruction-processing portion of the processor; and the second voltageis sufficient for the second portion of the processor to operate.
 4. Theprocessor of claim 3, wherein the processor transitions from the firstpower-saving mode to the normal operation mode responsive to aninterrupt signal.
 5. The processor of claim 3, wherein in the secondpower-saving mode: the first clock signal is inactive; the first voltageis reduced; and the second voltage is sufficient for the second portionof the processor to operate.
 6. The processor of claim 5, wherein theprocessor transitions from the second power-saving mode to the normaloperation mode responsive to a signal that is at least one of aninterrupt signal and a signal indicating that processing is to resume.7. The processor of claim 5, wherein the first voltage is reduced tozero.
 8. The processor of claim 5, wherein the state of theinstruction-processing portion of the processor is saved to a memorybefore the first voltage is reduced to a level that is not sufficient tomaintain the state.
 9. The processor of claim 8, wherein the memory isexternal to the processor.
 10. The processor of claim 1, wherein thesecond power area comprises an interrupt processor.
 11. The processor ofclaim 1, wherein the second power area comprises snoop circuitry. 12.The processor of claim 1, wherein the second power area comprises acache memory.
 13. The processor of claim 1, wherein the processortransitions to the first power-saving mode responsive to a determinationthat the instruction-processing portion is not needed soon.
 14. Theprocessor of claim 1, wherein the processor transitions to the secondpower-saving mode responsive to a determination that theinstruction-processing portion is not needed soon and theinstruction-processing portion has been taking long naps recently.
 15. Amethod, comprising: in a processor that comprises a first power areathat comprises an instruction-processing portion of the processor andoperates responsive to a first voltage and a first clock signal that aresupplied to the first power area, and a second power area that comprisesa second portion of the processor and operates responsive to a secondvoltage that is supplied to the second power area, operating the firstpower area of the processor in one of a normal operation mode when thefirst voltage is at a first level, a first power-saving mode when thefirst voltage is at a second level, and a second power-saving mode whenthe first voltage is at a third level.
 16. The method of claim 15,wherein operating the processor in the normal operation mode comprises:providing, for the first clock signal, an active clock signal;providing, for the first voltage, a voltage sufficient for theinstruction-processing portion of the processor to process instructions;and providing, for the second voltage, a voltage sufficient for thesecond portion of the processor to operate.
 17. The method of claim 16,wherein operating the processor in the first power-saving modecomprises: providing, for the first clock signal, an inactive clocksignal; providing, for the first voltage, a voltage sufficient tomaintain a state of the instruction-processing portion of the processor;and providing, for the second voltage, a voltage sufficient for thesecond portion of the processor to operate.
 18. The method of claim 17,further comprising: transitioning the processor from the firstpower-saving mode to the normal operation mode responsive to aninterrupt signal.
 19. The method of claim 17, wherein operating theprocessor in the second power-saving mode comprises: providing, for thefirst clock signal, an inactive clock signal; providing, for the firstvoltage, a reduced voltage; and providing, for the second voltage, avoltage sufficient for the second portion of the processor to operate.20. The method of claim 19, further comprising: transitioning theprocessor from the second power-saving mode to the normal operation moderesponsive to a signal that is not an interrupt signal.
 21. The methodof claim 19, wherein providing, in the second power saving mode, for thefirst voltage, a reduced voltage comprises providing zero volts.
 22. Themethod of claim 19, further comprising: saving the state of theinstruction-processing portion of the processor to a memory before thefirst voltage is reduced to a level that is not sufficient to maintainthe state.
 23. The method of claim 22, wherein the memory is external tothe processor.
 24. The method of claim 15, wherein the second power areacomprises an interrupt processor.
 25. The method of claim 15, whereinthe second power area comprises snoop circuitry.
 26. The method of claim15, wherein the second power area comprises a cache memory.
 27. Themethod of claim 15, further comprising: transitioning the processor tothe first power-saving mode responsive to a determination that theinstruction-processing portion is not needed soon.
 28. The method ofclaim 15, further comprising: transitioning the processor to the secondpower-saving mode responsive to a determination that theinstruction-processing portion is not needed soon and theinstruction-processing portion has been taking long naps recently.